mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 169

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

fetches a unique exception vector, 12, from the vector table.
Execution continues at the instruction address in the vector corresponding to the breakpoint
triggered. All interrupts are ignored while the processor is in emulator mode. The debug
interrupt handler can use supervisor instructions to save the necessary context such as the
state of all program-visible registers into a reserved memory area.
When debug interrupt operations complete, the RTE instruction executes and the processor
exits emulator mode. After the debug interrupt handler completes execution, the external
development system can use BDM commands to read the reserved memory locations.
The generation of another debug interrupt during the first instruction after the RTE exits
emulator mode is inhibited. This behavior is consistent with the existing logic involving
trace mode where the first instruction executes before another trace exception is generated.
Thus, all hardware breakpoints are disabled until the first instruction after the RTE
completes execution, regardless of the programmed trigger response.
5.6.1.1 Emulator Mode
Emulator mode is used to facilitate non-intrusive emulator functionality. This mode can be
entered in three different ways:
While operating in emulation mode, the processor exhibits the following properties:
The RTE instruction exits emulation mode. The processor status output port provides a
unique encoding for emulator mode entry (0xD) and exit (0x7).
5.6.2 Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM
commands. BDM commands may be executed while the processor is running, except those
following operations that access processor/memory registers:
• Setting CSR[EMU] forces the processor into emulator mode. EMU is examined
• A debug interrupt always puts the processor in emulation mode when debug
• Setting CSR[TRC] forces the processor into emulation mode when trace exception
• All interrupts are ignored, including level-7 interrupts.
• If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All
only if RSTI is negated and the processor begins reset exception processing. It can
be set while the processor is halted before reset exception processing begins. See
Section 5.5.1, “CPU Halt.”
interrupt exception processing begins.
processing begins.
memory accesses are forced into a specially mapped address space signaled by
TT = 0x2, TM = 0x5 or 0x6. This includes stack frame writes and the vector fetch
for the exception that forced entry into this mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 5. Debug Support
Go to: www.freescale.com
Real-Time Debug Support
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