mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 141

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Table 5-9 describes DBR fields.
Table 5-10 describes DBMR fields.
The DBR supports both aligned and misaligned references. Table 5-11 shows relationships
between processor address, access size, and location within the 32-bit data bus.
5.4.6 Program Counter Breakpoint/Mask Registers
The PC breakpoint register (PBR) defines an instruction address for use as part of the
trigger. This register’s contents are compared with the processor’s program counter register
when TDR is configured appropriately. PBR bits are masked by clearing corresponding
PBMR bits. Results are compared with the processor’s program counter register, as defined
in TDR. Figure 5-10 shows the PC breakpoint register.
31–0
31–0
Bits
Bits
Mask
Data
Name
Name
(PBR, PBMR)
Data breakpoint value. Contains the value to be compared with the data value from the processor’s
local bus as a breakpoint trigger.
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBR bit allows
the corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus.
Setting a DBMR bit causes that bit to be ignored.
Table 5-11. Access Size and Operand Data Location
Freescale Semiconductor, Inc.
Table 5-10. DBMR Field Descriptions
For More Information On This Product,
A[1:0]
Table 5-9. DBR Field Descriptions
00
01
10
11
0x
1x
xx
Chapter 5. Debug Support
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Access Size
Longword
Word
Word
Byte
Byte
Byte
Byte
Description
Description
Operand Location
D[31:24]
D[23:16]
D[31:16]
D[15:8]
D[15:0]
D[31:0]
D[7:0]
Programming Model
5-13