mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 183

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

6.2 Programming Model
The following sections describe the registers incorporated into the SIM.
6.2.1 SIM Register Memory Map
Table 6-1 shows the memory map for the SIM registers. The internal registers in the SIM
are memory-mapped registers offset from the MBAR address pointer defined in
MBAR[BA]. This supervisor-level register is described in Section 6.2.2, “Module Base
Address Register (MBAR).” Because SIM registers depend on the base address defined in
MBAR[BA], MBAR must be programmed before SIM registers can be accessed.
0x010–
MBAR
Offset
0x00C
0x03C
0x000
0x004
0x008
0x040
0x044
0x048
Default bus master park
Reset status register
PLL control (PLLCR)
register (MPARK)
Although external masters cannot access the MCF5307’s
on-chip memories or MBAR, they can access any of the SIM
memory map and peripheral registers, such as those belonging
to the interrupt controller, chip-select module, UARTs, timers,
DMA, and I
(RSR) [p. 6-5]
Pin assignment register (PAR) [p. 6-10]
[p. 6-11]
[31:24]
[p. 7-3]
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C.
Interrupt Control Registers (ICRs) [p. 9-3]
Interrupt Controller Registers [p. 9-2]
Table 6-1. SIM Registers
System protection
(SYPCR) [p. 6-8]
Chapter 6. SIM Overview
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control register
Interrupt pending register (IPR) [p. 9-6]
Interrupt mask register (IMR) [p. 9-6]
Reserved
[23:16]
NOTE:
Reserved
interrupt vector register
assignment register
Software watchdog
(IRQPAR) [p. 9-7]
(SWIVR) [p. 6-9]
Interrupt port
Reserved
Reserved
[15:8]
service register (SWSR)
Programming Model
Software watchdog
Autovector register
(AVR) [p. 9-5]
Reserved
[p. 6-9]
[7:0]
6-3