mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 197

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Chapter 7
Phase-Locked Loop (PLL)
This chapter describes configuration and operation of the phase-locked loop (PLL) module.
It describes in detail the registers and signals that support the PLL implementation.
7.1 Overview
The basic features of the MCF5307 PLL implementation are as follows:
The PLL module has the following three modes of operation:
Figure 7-1 shows the frequency relationships of PLL module clock signals.
z
• The PLL locks to the clock input (CLKIN) frequency. It provides a processor clock
• A buffered processor status clock (PSTCLK) is equal to the PCLK frequency, as
• Reset mode—In reset mode, the core/bus frequency ratio and other configuration
• Normal mode—During normal operations, the divide ratio is programmed at reset
• Reduced-power mode—In reduced-power mode, the high-speed processor core
(PCLK) that is twice the input clock frequency and a programmable system bus
clock output (BCLKO) that is 1/2, 1/3, or 1/4 the PCLK frequency.
indicated in Figure 7-1. This signal is made available for system development.
information is sampled. At reset, the PLL asserts the reset out signal, RSTO.
and is clock-multiplied to provide a maximum frequency of 90 MHz
clocks are turned off without losing the register contents so that the system can be
reenabled by an unmasked interrupt or reset.
DIVIDE[1:0]
FREQ[1:0]
CLKIN
RSTI
Freescale Semiconductor, Inc.
Figure 7-1. PLL Module Block Diagram
For More Information On This Product,
Chapter 7. Phase-Locked Loop (PLL)
CLKIN X 4
PLL
Go to: www.freescale.com
Divide
by 2
Divide by 2,
3, or 4
RSTO
PCLK
PSTCLK
BCLKO
7-1