mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 120

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Cache Registers
4.10.2 Access Control Registers (ACR0–ACR1)
The ACRs, Figure 4-9, assign control attributes, such as cache mode and write protection,
to specified memory regions. Registers are accessed with the MOVEC instruction with the
Rc encodings in Figure 4-9.
For overlapping regions, ACR0 takes priority. Data transfers to and from these registers are
longword transfers. Bits 12–7, 4, 3, 1, and 0 are always read as zeros.
4-22
27
26–25 —
24
23–11
10
9–8
7–6
5
4–0
Bits
DNFB
DCM
—
DW
—
CINVA
Name
HLCK
—
Half-cache lock mode
0 Normal operation. The cache allocates the lowest invalid way. If all ways are valid, the cache
1 Half-cache operation. The cache allocates to the lower invalid way of levels 2 and 3; if both are
This implementation allows maximum use of available cache memory and provides the flexibility
of setting HLCK before, during, or after allocations occur.
Reserved, should be cleared.
Cache invalidate all. Writing a 1 to this bit initiates entire cache invalidation. Once invalidation is
complete, this bit automatically returns to 0; it is not necessary to clear it explicitly. Note the
caches are not cleared on power-up or normal reset, as shown in Figure 4-4.
0 No invalidation is performed.
1 Initiate invalidation of the entire cache. The cache controller sequentially clears V and M bits in
Reserved, should be cleared.
Default noncacheable fill buffer. Determines if the fill buffer can store noncacheable accesses
0 Fill buffer not used to store noncacheable instruction accesses (16 or 32 bits).
1 Fill buffer used to store noncacheable accesses. The fill buffer is used only for normal (TT = 0)
Note that this feature can cause a coherency problem for self-modifying code. If DNFB = 1 and a
cache-inhibited access uses the fill buffer, instructions remain valid in the fill buffer until a
cache-invalidate-all instruction, another cache-inhibited burst, or a miss that initiates a fill. A write
to the line in the fill buffer goes to the external bus without updating or invalidating the buffer.
Subsequent reads of that written data are serviced by the fill buffer and receive stale information.
Default cache mode. Selects the default cache mode and access precision as follows:
00 Cacheable, write-through
01 Cacheable, copy-back
10 Cache-inhibited, precise exception model
11 Cache-inhibited, imprecise exception model. Precise and imprecise modes are described in
Reserved, should be cleared.
Default write protect. Use of this bit is described in Section 4.9.1, “Caching Modes.”
0 Read and write accesses permitted
1 Write accesses not permitted
Reserved, should be cleared.
allocates the way pointed at by the counter and then increments this counter modulo-4.
valid, the cache allocates to way 2 if the high-order bit of the round-robin counter is zero;
otherwise, it allocates way 3 and increments the round-robin counter modulo-2. This locks the
content of ways 0 and 1. Ways 0 and 1 are still updated on write hits and may be pushed or
cleared by specific cache push/invalidate instructions.
all sets. Subsequent accesses stall until the invalidation is finished, at which point, this bit is
automatically cleared. In copyback mode, the cache should be flushed using a CPUSHL
instruction before setting this bit.
instruction reads of a noncacheable region. Instructions are loaded into the fill buffer by a burst
access (same as a line fill). They stay in the buffer until they are displaced, so subsequent
accesses may not appear on the external bus.
Section 4.9.2, “Cache-Inhibited Accesses.”
Table 4-4. CACR Field Descriptions (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MCF5307 User’s Manual
Description