mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 291

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

12.5.2.2 Single-Address Transfers
Single-address transfers consist of one DMA bus cycle, allowing either a read or a write
cycle to occur. The DMA controller begins a single-address transfer sequence when
DCR[SAA] is set during a DMA request. If no error condition exists, DSR[REQ] is set.
When the channel is enabled, DSR[BSY] is set and REQ is cleared. SAR contents are then
driven onto the address bus and the value of DCR[S_RW] is driven on R/W. The BCR
decrements on each successful address access until it is zero, when DSR[DONE] is set.
If a termination error occurs, DSR[BES,DONE] are set and DMA transactions stop.
12.5.3 Channel Initialization and Startup
Before a block transfer starts, channel registers must be initialized with information
describing configuration, request-generation method, and the data block.
12.5.3.1 Channel Prioritization
The four DMA channels are prioritized in ascending order (channel 0 having highest
priority and channel 3 having the lowest) or as determined by DCR[BWC]. If BWC for a
DMA channel is 000, that channel has priority only over the channel immediately
preceding it. For example, if DCR3[BWC] = 000, DMA channel 3 has priority over DMA
channel 2 (assuming DCR2[BWC] ≠ 000) but not over DMA channel 1.
If DCR1[BWC] = DCR2[BWC] = 000, DMA 1 has priority over DMA 0 and DMA 2.
DCR2[BWC] = 000 in this case does not affect prioritization.
Prioritization of simultaneous external requests is either ascending or as determined by
each channel’s BWC bits as described in the previous paragraphs.
12.5.3.2 Programming the DMA Controller Module
Note the following general guidelines for programming the DMA:
The SAR is loaded with the source (read) address. If the transfer is from a peripheral device
to memory, the source address is the location of the peripheral data register. If the transfer
• Dual-address write—The DMA controller drives the DAR value onto the address
• No mechanism exists to prevent writes to control registers during DMA accesses.
• If the BWC of sequential channels are equal, channel priority is in ascending order.
bus. If DCR[DINC] is set, DAR increments by the appropriate number of bytes at
the completion of a successful write cycle. The BCR decrements by the appropriate
number of bytes. DSR[DONE] is set when BCR reaches zero. If the BCR is greater
than zero, another read/write transfer is initiated. If the BCR is a multiple of
DCR[BWC], the DMA request signal is negated until termination of the bus cycle
to allow the internal arbiter to switch masters.
If a termination error occurs, DSR[BES,DONE] are set and DMA transactions stop.
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 12. DMA Controller Module
Go to: www.freescale.com
DMA Controller Module Functional Description
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