mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 146

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Background Debug Mode (BDM)
DSI must meet the required input setup and hold timings and the DSO is specified as a delay
relative to the rising edge of the processor clock. See Table 5-1. The development system
serves as the serial communication channel master and must generate DSCLK.
The serial channel operates at a frequency from DC to 1/5 of the processor frequency. The
channel uses full-duplex mode, where data is sent and received simultaneously by both
master and slave devices. The transmission consists of 17-bit packets composed of a
status/control bit and a 16-bit data word. As shown in Figure 5-13, all state transitions are
enabled on a rising edge of the processor clock when DSCLK is high; that is, DSI is
sampled and DSO is driven.
DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is
sampled on the rising edge of the processor CLK as well as the DSI. DSO is delayed from
the DSCLK-enabled CLK rising edge (registered after a BDM state machine state change).
All events in the debug module’s serial state machine are based on the processor clock
rising edge. DSCLK must also be sampled low (on a positive edge of CLK) between each
bit exchange. The MSB is transferred first. Because DSO changes state based on an
internally-recognized rising edge of DSCLK, DSDO cannot be used to indicate the start of
a serial transfer. The development system must count clock cycles in a given transfer.
C1–C4 are described as follows:
5-18
• C1—First synchronization cycle for DSI (DSCLK is high).
• C2—Second synchronization cycle for DSI (DSCLK is high).
• C3—BDM state machine changes state depending upon DSI and whether the entire
• C4—DSO changes to next value.
BDM State
CPU CLK
PSTCLK
input data transfer has been transmitted.
Machine
DSCLK
DSO
DSI
A not-ready response can be ignored except during a
memory-referencing cycle. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
Figure 5-13. BDM Serial Interface Timing
Freescale Semiconductor, Inc.
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Current State
Past
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C1
Current
MCF5307 User’s Manual
C2
NOTE:
C3
C4
Next State
Current
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