mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 54

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Status register (SR)
Vector base register
(VBR)
Cache configuration
register (CACR)
Access control
registers (ACR0/1)
RAM base address
register (RAMBAR)
Module base address
register (MBAR)
Programming Model, Addressing Modes, and Instruction Set
1.4.2 User Registers
The user programming model is shown in Figure 1-4 and summarized in Table 1-1.
1.4.3 Supervisor Registers
Table 1-2 summarizes the MCF5307 supervisor-level registers.
Data registers
(D0–D7)
Address registers
(A0–A7)
Program counter
(PC)
Condition code
register (CCR)
MAC status
register (MACSR)
Accumulator
(ACC)
Mask register
(MASK)
1-14
Register
Register
These 32-bit registers are for bit, byte, word, and longword operands. They can also be used as
index registers.
These 32-bit registers serve as software stack pointers, index registers, or base address
registers. The base address registers can be used for word and longword operations. A7
functions as a hardware stack pointer during stacking for subroutine calls and exception handling.
Contains the address of the instruction currently being executed by the MCF5307 processor
The CCR is the lower byte of the SR. It contains indicator flags that reflect the result of a previous
operation and are used for conditional instruction execution.
Defines the operating configuration of the MAC unit and contains indicator flags from the results
of MAC instructions.
General-purpose register used to accumulate the results of MAC operations
General-purpose register provides an optional address mask for MAC instructions that fetch
operands from memory. It is useful in the implementation of circular queues in operand memory.
signaling the operating state of the ColdFire processor. The lower byte of the SR is the CCR, as
shown in Figure 1-4.
Defines the upper 12 bits of the base address of the exception vector table used during exception
processing. The low-order 20 bits are forced to zero, locating the vector table on 0-modulo-1
Mbyte address.
Defines the operating modes of the Version 4 cache memories. Control fields configuring the
instruction, data, and branch cache are provided by this register, along with the default attributes
for the 4-Gbyte address space.
Define address ranges and attributes associated with various memory regions within the 4-Gbyte
address space. Each ACR defines the location of a given memory region and assigns attributes
such as write-protection and cache mode (copyback, write-through, cacheability). Additionally,
CACR fields assign default attributes to the instruction and data memory spaces.
Provide the logical base address for the 4-Kbyte SRAM module and define attributes and access
types allowed for the SRAM.
Defines the logical base address for the memory-mapped space containing the control registers
for the on-chip peripherals.
The upper byte of the SR provides interrupt information in addition to a variety of mode indicators
Freescale Semiconductor, Inc.
Table 1-2. Supervisor-Level Registers
For More Information On This Product,
Table 1-1. User-Level Registers
Go to: www.freescale.com
MCF5307 User’s Manual
Description
Description