mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 210

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Programming Model
8.5.3 I
The I2CR is used to enable the I
govern operation as a slave or a master.
Table 8-4 describes I2CR fields.
7
6
5
4
3
2
1–0
8-8
Bits
IEN
IIEN
MSTA
MTX
TXAK
—
Name
RSTA Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes loss of
2
C Control Register (I2CR)
I
middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the
next start condition is detected. Master mode is not aware that the bus is busy; so initiating a start
cycle may corrupt the current bus cycle, ultimately causing either the current master or the I
module to lose arbitration, after which bus operation returns to normal.
0 The module is disabled, but registers can still be accessed.
1 The I
I
0 I
1 I
Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating a
STOP signal.
0 Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.
1 Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode.
Transmit/receive mode select bit. Selects the direction of master and slave transfers.
0 Receive
1 Transmit. When a slave is addressed, software should set MTX according to I2SR[SRW]. In
Transmit acknowledge enable. Specifies the value driven onto SDA during acknowledge cycles for
both master and slave receivers. Note that writing TXAK applies only when the I
0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
1 No acknowledge signal response is sent (that is, acknowledge bit = 1).
arbitration.
0 No repeat start
1 Generates a repeated START condition.
Reserved, should be cleared.
2
2
C enable. Controls the software reset of the entire I
C interrupt enable.
Address
master mode, MTX should be set according to the type of transfer required. Therefore, for address
cycles, MTX is always 1.
2
2
C module interrupts are disabled, but currently pending interrupt condition are not cleared.
C module interrupts are enabled. An I
Reset
Field
R/W
2
C module is enabled. This bit must be set before any other I2CR bits have any effect.
Freescale Semiconductor, Inc.
IEN
Figure 8-7. I
7
For More Information On This Product,
Table 8-4. I2CR Field Descriptions
IIEN
6
2
Go to: www.freescale.com
C module and the I
MCF5307 User’s Manual
MSTA
2
C Control Register (I2CR)
5
MBAR + 0x288
MTX
0000_0000
Read/Write
4
2
C interrupt occurs if I2SR[IIF] is also set.
Description
TXAK
3
2
C interrupt. It also contains bits that
2
C module. If the module is enabled in the
RSTA
2
1
—
0
2
C bus is a receiver.
2
C