mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 425

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Chapter 19
IEEE 1149.1 Test Access Port (JTAG)
This chapter describes configuration and operation of the MCF5307 JTAG test
implementation. It describes the use of JTAG instructions and provides information on how
to disable JTAG functionality.
19.1 Overview
The MCF5307 dedicated user-accessible test logic is fully compliant with the publication
Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1. Use the
following description in conjunction with the supporting IEEE document listed above. This
section includes the description of those chip-specific items that the IEEE standard requires
as well as those items specific to the MCF5307 implementation.
The MCF5307 JTAG test architecture supports circuit board test strategies based on the
IEEE standard. This architecture provides access to all data and chip control pins from the
board-edge connector through the standard four-pin test access port (TAP) and the JTAG
reset pin, TRST. Test logic design is static and is independent of the system logic except
where the JTAG is subordinate to other complimentary test modes, as described in
Chapter 5, “Debug Support.” When in subordinate mode, JTAG test logic is placed in reset
and the TAP pins can be used for other purposes, as described in Table 19-1.
The MCF5307 JTAG implementation can do the following:
• Perform boundary-scan operations to test circuit board electrical continuity
• Bypass the MCF5307 by reducing the shift register path to a single cell
• Set MCF5307 output drive pins to fixed logic values while reducing the shift register
• Sample MCF5307 system pins during operation and transparently shift out the result
• Protect MCF5307 system output and input pins from backdriving and random
path to a single cell
toggling (such as during in-circuit testing) by placing all system pins in high-
impedance state
IEEE Standard 1149.1 may interfere with system designs that do
not incorporate JTAG capability. Section 19.6, “Disabling IEEE
Standard 1149.1 Operation,” describes precautions for ensuring
that this logic does not affect system or debug operation.
Chapter 19. IEEE 1149.1 Test Access Port (JTAG)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
NOTE:
19-1