mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 286

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Reset
1
Address
DMA Controller Module Programming Model
DSR[DONE], shown in Figure 12-9, is set when the block transfer is complete.
When a transfer sequence is initiated and BCRn[BCR] is not divisible by 16, 4, or 2 when
the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set
and no transfer occurs. See Section 12.4.5, “DMA Status Registers (DSR0–DSR3).”
12.4.4 DMA Control Registers (DCR0–DCR3)
DCRn, Figure 12-8, is used for configuring the DMA controller module. Note that
DCR[AT] is available only if BCR24BIT = 1.
Table 12-3 describes DCR fields.
Field
Addr
R/W
31
30
12-8
Bits
Available only if BCR24BIT = 1, otherwise reserved.
Reset
Reset
Bit
Field INT EEXT
Field AT
R/W
R/W
15
INT
EEXT
Name
31
15
0
1
14
30
14
Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a
transfer or by the occurrence of an error condition.
0 No interrupt is generated.
1 Internal interrupt signal is enabled.
Enable external request. Care should be taken because a collision can occur between the START
bit and DREQ when EEXT = 1.
0 External request is ignored.
1 Enables external request to initiate transfer. Internal request is always enabled. It is initiated by
writing a 1 to the START bit.
13
CS
29
Figure 12-8. DMA Control Registers (DCRn)
Freescale Semiconductor, Inc.
AA
28
12
Table 12-3. DCRn Field Descriptions
For More Information On This Product,
Figure 12-7. BCRn—BCR24BIT = 0
27
11
MBAR + 0x30C, 0x34C, 0x38C, 0x3AC
BWC
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MBAR + 0x308, 0x348, 0x388, 0x3A8
MCF5307 User’s Manual
10
0000_0000_0000_0000
25
0000_0000_0000_0000
9
SAA S_RW SINC
24
BCR
R/W
R/W
8
Description
23
N/A
—
7
22
6
21
SSIZE
5
20
4
DINC
19
3
18
DSIZE
2
17
1
START
16
0
0