mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 206

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

I
Instead of signalling a STOP, the master can repeat the START signal, followed by a calling
command, (A in Figure 8-3). A repeated START occurs when a START signal is generated
without first generating a STOP signal to end the communication.
The master uses a repeated START to communicate with another slave or with the same
slave in a different mode (transmit/receive mode) without releasing the bus.
8.4.1 Arbitration Procedure
If multiple devices simultaneously request the bus, the bus clock is determined by a
synchronization procedure in which the low period equals the longest clock-low period
among the devices and the high period equals the shortest. A data arbitration procedure
8-4
2
C Protocol
SCL
SDA
3. Data transfer—When successful slave addressing is achieved, the data transfer can
4. STOP signal—The master can terminate communication by generating a STOP
START
Signal
The slave whose address matches that sent by the master pulls SDA low at the ninth
clock (D) to return an acknowledge bit.
proceed (E) on a byte-by-byte basis in the direction specified by the R/W bit sent by
the calling master.
Data can be changed only while SCL is low and must be held stable while SCL is
high, as Figure 8-2 shows. SCL is pulsed once for each data bit, with the msb being
sent first. The receiving device must acknowledge each byte by pulling SDA low at
the ninth clock; therefore, a data byte transfer takes nine clock pulses.
If it does not acknowledge the master, the slave receiver must leave SDA high. The
master can then generate a STOP signal to abort the data transfer or generate a
START signal (repeated start, shown in Figure 8-3) to start a new calling sequence.
If the master receiver does not acknowledge the slave transmitter after a byte
transmission, it means end-of-data to the slave. The slave releases SDA for the
master to generate a STOP or START signal.
signal to free the bus. A STOP signal is defined as a low-to-high transition of SDA
while SCL is at logical high (F). Note that a master can generate a STOP even if the
slave has made an acknowledgment, at which point the slave must release the bus.
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
msb
1
2
Calling Address
3
4
Freescale Semiconductor, Inc.
5
For More Information On This Product,
6
Figure 8-3. Repeated START
7
Go to: www.freescale.com
R/W
lsb
MCF5307 User’s Manual
8
ACK
Bit
9
XX
Repeated
START
Signal
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
msb
A
1
2
New Calling Address
Stop
3
4
5
6
7
R/W No
lsb
8
ACK
Bit
9
STOP
Signal