mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 80

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

1
TST
UNLK
WDDATA
Instruction
1
execution by setting CSR[UHE].
By default the HALT instruction is a supervisor-mode instruction; however, it can be configured to allow user-mode
CPUSHL
HALT
MOVE from SR
MOVE to SR
MOVEC
RTE
STOP
WDEBUG
Instruction Timing
Table 2-8 describes supervisor-mode instructions.
2.7 Instruction Timing
The timing data presented in this section assumes the following:
2-40
The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE].
Instruction
• The OEP is loaded with the opword and all required extension words at the
• The OEP experiences no sequence-related pipeline stalls. For the MCF5307, the
1
beginning of each instruction execution. This implies that the OEP spends no time
waiting for the IFP to supply opwords and/or extension words.
most common example of this type of stall involves consecutive store operations,
excluding the MOVEM instruction. For all store operations (except MOVEM),
<ea>y
Ax
<ea>y
Operand Syntax
Table 2-7. User-Mode Instruction Set Summary (Continued)
(An)
none
SR, Dx
Dy,SR
#<data>,SR
Ry,Rc
None
#<data>
<ea-2>y
Operand Syntax Operand Size
Table 2-8. Supervisor-Mode Instruction Set Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
.B,.W,.L
Unsized
.B,.W,.L
Unsized
Unsized
.W
.W
.L
Unsized
.W
.L
Operand Size
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MCF5307 User’s Manual
Invalidate instruction cache line
Push and invalidate data cache line
Push data cache line and invalidate (I,D)-cache lines
Enter halted state
SR → Dx
Source → SR
Ry → Rc
Rc
0x002
0x004
0x005
0x006
0x007
0x801
0xC04 RAM base address register 0 (RAMBAR0)
0xC05 RAM base address register 1 (RAMBAR1)
(SP+2) → SR; SP+4 → SP; (SP) → PC; SP + formatfield  SP
Immediate data → SR; enter stopped state
<ea-2>y → debug module
Set condition codes
Ax →SP; (SP) → Ax; SP + 4 → SP
<ea>y →DDATA port
Register Definition
Cache control register (CACR)
Access control register 0 (ACR0)
Access control register 1 (ACR1)
Access control register 2 (ACR2)
Access control register 3 (ACR3)
Vector base register (VBR)
Operation
Operation