mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 391

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

18.4 Data Transfer Operation
Data transfers between the MCF5307 and other devices involve the following signals:
The address bus, write data, TS, and all attribute signals change on the rising edge of
BCLKO. Read data is latched into the MCF5307 on the rising edge of BCLKO. AS, CSx,
OE, and BE/BWE change on the falling edge.
The MCF5307 bus supports byte, word, and longword operand transfers and allows
accesses to 8-, 16-, and 32-bit data ports. Transfer parameters such as port size, the number
of wait states for the external slave being accessed, and whether internal transfer
termination is enabled, can be programmed in the chip-select control registers (CSCRs) and
DRAM control registers (DACRs).
For aligned transfers larger than the port size, SIZ[1:0] behaves as follows:
Table 18-2 shows encoding for SIZ[1:0].
Figure 18-2 shows the byte lanes that external memory should be connected to and the
sequential transfers if a longword is transferred for three port sizes. For example, an 8-bit
memory should be connected to D[31:24] (BE0). A longword transfer takes four transfers
on D[31:24], starting with the MSB and going to the LSB.
• Address bus (A[31:0])
• Data bus (D[31:0])
• Control signals (TS and TA)
• AS, CSx, OE, BE/BWE
• Attribute signals (R/W, SIZ, TT, TM, and TIP)
• If bursting is used, SIZ[1:0] stays at the size of transfer.
• If bursting is inhibited, SIZ[1:0] first shows the size of the transfer and then shows
the port size.
Freescale Semiconductor, Inc.
Table 18-2. Bus Cycle Size Encoding
For More Information On This Product,
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01
10
11
Chapter 18. Bus Operation
SIZ[1:0]
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Longword
Byte
Word
Line
Port Size
Data Transfer Operation
18-3