mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 287

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

29
28
27–25 BWC
24
23
22
21–20 SSIZE
19
18–17 DSIZE
Bits
CS
AA
SAA
S_RW
SINC
DINC
Name
Cycle steal.
0 DMA continuously makes read/write transfers until the BCR decrements to 0.
1 Forces a single read/write transfer per request. The request may be internal by setting the START
Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is,
transfers are optimized based on the address and size. See Section 12.5.4.2, “Auto-Alignment.”
0 Auto-align disabled
1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned;
Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count reaches
a multiple of the BWC value, the DMA releases the bus. For example, if BCR24BIT is 0, BWC is
001 (512 bytes or value of 0x0200), and BCR is 0x1000, the bus is relinquished after BCR values of
0x2000, 0x1E00, 0x1C00, 0x1A00, 0x1800, 0x1600, 0x1400, 0x1200, 0x1000, 0x0E00, 0x0C00,
0x0A00, 0x0800, 0x0600, 0x0400, and 0x0200. If BCR24BIT is 0, BWC is 110, and BCR is 33000,
the bus is released after 232 bytes because the BCR is at 32768, a multiple of 16384.
BWC
000
001
010
011
100
101
110
111
Single-address access. Determines whether the DMA channel is in dual- or single-address mode
0 Dual-address mode.
1 Single-address mode. The DMA provides an address from the SAR and directional control, bit
Single-address access read/write value. Valid only if SAA = 1. Specifies the value of the read signal
during single-address accesses. This provides directional control to the bus controller.
0 Forces the read signal to 0.
1 Forces the read signal to 1.
Source increment. Controls whether a source address increments after each successful transfer.
0 No change to SAR after a successful transfer.
1 The SAR increments by 1, 2, 4, or 16, as determined by the transfer size.
Source size. Determines the data size of the source bus cycle for the DMA control module.
00 Longword
01 Byte
10 Word
11 Line
Destination increment. Controls whether a destination address increments after each successful
transfer.
0 No change to the DAR after a successful transfer.
1 The DAR increments by 1, 2, 4, or 16, depending upon the size of the transfer.
Destination size. Determines the data size of the destination bus cycle for the DMA controller.
00 Longword
01 Byte
10 Word
11 Line
bit, or external by asserting DREQ.
otherwise, destination accesses are auto-aligned. Source alignment takes precedence over
destination alignment. If auto-alignment is enabled, the appropriate address register increments,
regardless of DINC or SINC.
S_RW, to allow two peripherals (one might be memory) to exchange data within a single access.
Data is not stored by the DMA.
Table 12-3. DCRn Field Descriptions (Continued)
BCR24BIT = 0
DMA has priority. It does not negate its request until its transfer completes.
512
1024
2048
4096
8192
16384
32768
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 12. DMA Controller Module
Go to: www.freescale.com
BCR24BIT = 1
16384
32768
65536
131072
262144
524288
1048576
Description
DMA Controller Module Programming Model
12-9