mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 292

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
DMA Controller Module Functional Description
is from memory to either a peripheral device or memory, the source address is the starting
address of the data block. This can be any aligned byte address. In single-address mode, this
data register is used regardless of transfer direction.
The DAR should contain the destination (write) address. If the transfer is from a peripheral
device to memory, or memory to memory, the DAR is loaded with the starting address of
the data block to be written. If the transfer is from memory to a peripheral device, DAR is
loaded with the address of the peripheral data register. This address can be any aligned byte
address. DAR is not used in single-address mode.
SAR and DAR change after each cycle depending on DCR[SSIZE,DSIZE,SINC,DINC]
and on the starting address. Increment values can be 1, 2, 4, or 16 for byte, word, longword,
or line transfers, respectively. If the address register is programmed to remain unchanged
(no count), the register is not incremented after the data transfer.
BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented
by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. DSR must be
cleared for channel startup.
As soon as the channel has been initialized, it is started by writing a one to DCR[START]
or asserting DREQ, depending on the status of DCR[EEXT]. Programming the channel for
internal request causes the channel to request the bus and start transferring data
immediately. If the channel is programmed for external request, DREQ must be asserted
before the channel requests the bus.
Changes to DCR are effective immediately while the channel is active. To avoid problems
with changing a DMA channel setup, write a one to DSR[DONE] to stop the DMA channel.
12.5.4 Data Transfer
This section includes timing diagrams that illustrate the interaction of signals in DMA data
transfers. It also describes auto-alignment and bandwidth control.
12.5.4.1 External Request and Acknowledge Operation
Channels 0 and 1 initiate transfers to an external module by means of DREQ[1:0]. The
request for channels 2 and 3 are connected internally to the UART0 and UART1 interrupt
signals, respectively. If DCR[EEXT] = 1 and the channel is idle, the DMA initiates a
transfer when DREQ is asserted.
Figure 12-11 shows the minimum 4-clock cycle delay from when DREQ is sampled
asserted to when a DMA bus cycle begins. This delay may be longer, depending on DMA
priority, bus arbitration, DRAM refresh operations, and other factors.
12-14
MCF5307 User’s Manual
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