mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 48

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
ColdFire Module Description
1.3.1.5 8-Kbyte Unified Cache
The MCF5307 architecture includes an 8-Kbyte unified cache. This four-way,
set-associative cache provides pipelined, single-cycle access on cached instructions and
operands.
As with all ColdFire caches, the cache controller implements a non-lockup, streaming
design. The use of processor-local memories decouples performance from external
memory speeds and increases available bandwidth for external devices or the on-chip
4-channel DMA.
The cache implements line-fill buffers to optimize 16-byte line burst accesses. Additionally,
the cache supports copyback, write-through, or cache-inhibited modes. A 4-entry, 32-bit
buffer is used for cache line push operations and can be configured for deferred write
buffering in write-through or cache-inhibited modes.
1.3.1.6 Internal 4-Kbyte SRAM
The 4-Kbyte on-chip SRAM module provides pipelined, single-cycle access to memory
regions mapped to these devices. The memory can be mapped to any 0-modulo-32K
location in the 4-Gbyte address space. The SRAM module is useful for storing time-critical
functions, the system stack, or heavily-referenced data operands.
1.3.2 DRAM Controller
The MCF5307 DRAM controller provides a direct interface for up to two blocks of DRAM.
The controller supports 8-, 16-, or 32-bit memory widths and can easily interface to PC-100
DIMMs. A unique addressing scheme allows for increases in system memory size without
rerouting address lines and rewiring boards. The controller operates in normal mode or in
page mode and supports SDRAMs and EDO DRAMs.
1.3.3 DMA Controller
The MCF5307 provides four fully programmable DMA channels for quick data transfer.
Dual- and single-address modes support bursting and cycle steal. Data transfers are 32 bits
long with packing and unpacking supported along with an auto-alignment option for
efficient block transfers. Automatic block transfers from on-chip serial UARTs are also
supported through the DMA channels.
1.3.4 UART Modules
The MCF5307 contains two UARTs, which function independently. Either UART can be
clocked by the system bus clock, eliminating the need for an external crystal. Each UART
module interfaces directly to the CPU, as shown in Figure 1-2.
1-8
MCF5307 User’s Manual
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