mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 190

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

PARn = 0 PP15 PP14 PP13 PP12 PP11 PP10 PP9 PP8
PARn = 1 A31
Address
Reset Determined by driving D4/ADDR_CONFIG with a 1 or 0 when RSTI negates. The system is configured as PP[15:0] if
Field PAR15 PAR14 PAR13 PAR12 PAR11 PAR10 PAR9 PAR8 PAR7 PAR6
R/W
Programming Model
6.2.8 PLL Clock Control for CPU STOP Instruction
The SIM contains the PLL clock control register, which is described in detail in
Section 7.2.4, “PLL Control Register (PLLCR).” PLLCR[ENBSTOP,PLLIPL] are
significant to the operation of the SIM, and are described as follows:
6.2.9 Pin Assignment Register (PAR)
The pin assignment register (PAR), Figure 6-8, allows the selection of pin assignments.
6-10
• PLLCR[ENBSTOP] must be set for the ColdFire CPU STOP instruction to be
• PLLCR[PLLIPL] determines the minimum level at which an interrupt (decoded as
D4 is low; otherwise alternate pin functions selected by PAR = 1 are used.
15
acknowledged. This bit is cleared at reset and must be set for the MCF5307 to enter
low-power modes. The CPU STOP instruction stops only clocks to the core
processor. All internal modules remain clocked and can generate interrupts to restart
the ColdFire core. For example, the on-chip timer can be used to interrupt the
processor after a given timer countdown.
an interrupt priority level or IPL) must occur to awaken the PLL. The PLL then turns
clocks back on to the core processor and interrupt exception processing takes place.
Table 6-5 describes PLLIPL settings to be compared against the interrupt ranges that
awaken the core processor from a CPU STOP instruction.
A30
14
A29
13
Figure 6-8. Pin Assignment Register (PAR)
A28
12
Freescale Semiconductor, Inc.
For More Information On This Product,
A27
PLLIPL
11
Table 6-5. PLLIPL Settings
000
001
010
011
100
101
110
111
Go to: www.freescale.com
A26
MCF5307 User’s Manual
10
Address MBAR + 0x004
A25
9
Any interrupts can wake core
Interrupts 2–7
Interrupts 3–7
Interrupts 4–7
Interrupts 5–7
Interrupts 6–7
Interrupt 7 only
No interrupts can wake core
A24
8
R/W
Description
PP7
TIP DREQ0 DREQ1 TM2
7
PP6
6
PAR5 PAR4 PAR3
PP5
5
PP4
4
TM1
PP3
3
PAR2 PAR1 PAR0
TM0
PP2
2
PP1 PP0
TT1
1
TT0
0