mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 121

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Table 4-5 describes ACRn fields.
Reset
31–24
23–16
15
14–13
12–7
6–5
4–3
2
1–0
Field
I
R/W
Bits
Rc
31
Address
Address
Name
mask
base
CM
—
—
W
—
E
S
Address Base
The SIM MBAR region should be mapped as cache-inhibited
through an ACR.
Address base. Compared with address bits A[31:24]. Eligible addresses that match are
assigned the access control attributes of this register.
Address mask. Setting a mask bit causes the corresponding address base bit to be ignored.
The low-order mask bits can be set to define contiguous regions larger than 16 Mbytes. The
mask can define multiple noncontiguous regions of memory.
Enable. Enables or disables the other ACRn bits.
0 Access control attributes disabled
1 Access control attributes enabled
Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this
address range or if the type of access is a don’t care.
00 Match addresses only in user mode
01 Match addresses only in supervisor mode
1x Execute cache matching on all accesses
Reserved; should be cleared.
Cache mode. Selects the cache mode and access precision. Precise and imprecise modes are
described in Section 4.9.2, “Cache-Inhibited Accesses.”
00 Cacheable, write-through
01 Cacheable, copyback
10 Cache-inhibited, precise
11 Cache-inhibited, imprecise
Reserved, should be cleared.
Write protect. Selects the write privilege of the memory region.
0 Read and write accesses permitted
1 Write accesses not permitted
Reserved, should be cleared.
Figure 4-9. Access Control Register Format (ACRn)
Uninitialized
Freescale Semiconductor, Inc.
24 23
For More Information On This Product,
Table 4-5. ACRn Field Descriptions
Address Mask
Chapter 4. Local Memory
Go to: www.freescale.com
Write (R/W by debug module)
ACR0: 0x004; ACR1: 0x005
NOTE:
16 15 14 13 12
Description
E
0
S
—
Uninitialized
7
6
CM
Cache Registers
5
4
—
3
W
2
4-23
1
—
0