tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 20

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.
3.1 Reset Operation
Processor Core
(Note 1) Set the RESET pin to "0" before turning the power on. Perform the reset
after the power supply voltage has stabilized sufficiently within the operating range.
(Note 2) The reset operation can alter the internal RAM state, but does not alter data
in the backup RAM.
(Note 3) After turning the power on, make sure that the power supply voltage and
oscillation have stabilized, wait for 500 μs or longer, and perform the reset.
(Note 4) In the FLASH program, the reset period of 0.5 μs or longer is required
independently of the system clock.
The TMP19A61 has a high-performance 32-bit processor core (TX19A processor core). For
information on the operations of this processor core, please refer to the "TX19A Family
Architecture."
This chapter describes the functions unique to the TMP19A61 that are not explained in that
document.
To reset the device, ensure that the power supply voltage is in the operating voltage range, the
oscillation of the internal high-frequency oscillator has stabilized at the specified frequency and
that the
MHz operation).
Note that the PLL multiplication clock is quadrupled and the clock gear is initialized to the 1/8
mode during the reset period.
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RESET
When the reset request is authorized, the system control coprocessor (CP0) register of
the TX19A processor core is initialized. For further details, please refer to the chapter
about architecture.
After the reset exception handling is executed, the program branches off to the
exception handler. The address to which the program branches off (address where
exception handling starts) is called an exception vector address. This exception vector
address of a reset exception (for example, non-maskable interrupt) is 0xBFC0_0000H
(virtual address).
The register of the internal I/O is initialized.
The port pin (including the pin that can also be used by the internal I/O) is set to a
general-purpose input or output port mode.
input has been "0" for at least 12 system clocks (1.78 μs during external 13.5
TMP19A61 (rev1.0)-3-19
TMP19A61