tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 259

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.4.4 Channel Operation
A channel is activated if the Str bit of the CCRn is set to "1".
When a channel is activated, a configuration error check is conducted and the channel is put into a
standby mode if no error is detected. If an error is detected, the channel is gone into the abnormal
completion. When a channel goes into a standby mode, the Act bit of the CSRn of that channel
becomes "1".
A transfer request is generated immediately if a channel is programmed to start operation in response
to an internal transfer request. Then the DMAC acquires bus control authority and starts to transfer
data. The DMAC acquires bus control authority after INTDREQn or DREQn is asserted and starts to
transfer data if a channel is programmed to start operation in response to an external transfer request.
A channel is activated if the Str bit of the CCRn in each channel is set to "1." If a channel is activated,
an activation check is conducted and the channel is put into a standby mode if no error is detected.
The DMAC acquires bus control authority and starts to transfer data if a transfer request is generated
when a channel is in a standby mode.
Channel operation is completed either normally or abnormally (e.g. occurrence of an error). One of
the conditions is indicated to the CSRn.
Start of channel operation
Completion of channel operation
A channel completes operation either normally or abnormally and one of these states is indicated to
the CSRn.
Channel operation does not start and the completion of operation is considered to be abnormal
completion if "1" is set to the Str bit of the CCRn register when the NC or AbC bit of the CSRn register
is "1,"
Normal completion
Abnormal completion
Channel operation is considered to have been completed normally in the case shown below. For
the normally completed channel operation, it needs to be completed after the transfer of a unit of
data (value specified in the TrSiz field of CCRn) is completed successfully.
Cases of abnormal completion of DMAC operation are as follows:
•
•
A configuration error occurs if there is a mistake in the DMA transfer setting. Because a
configuration error occurs before data transfer begins, values specified in SARn, DARn and
BCRn remain the same as when they were initially specified. If channel operation is completed
abnormally due to a configuration error, the AbC bit of the CSRn is set to "1" along with the
Conf bit. Causes of a configuration error are as follows:
When the contents of BCRn become 0 and data transfer is completed.
Completion due to a configuration error
− Both SIO and DIO were set to "1."
− The Str bit of CCRn was set to "1" when the NC bit or AbC bit of CSRn was "1."
− A value that is not an integer multiple of the unit of data was set for BCRn.
− A value that is not an integer multiple of the unit of data was set for SARn or DARn.
TMP19A61 (rev1.0)10-258
TMP19A61