tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 30

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.6 Prescaler Clock Controller
5.7 Clock Multiplication Circuit (PLL)
Each internal I/O (TMRB0 to 23, TMRCA to B, SIO0 to A and SBI0 to 1) has a prescaler for
dividing a clock. The clock φ T0 to be input to each prescaler is obtained by selecting the "fperiph"
clock, which is divided according to the setting of SYSCR0<PRCK1:0>, from the
SYSCR1<FPSEL>. After the controller is reset, fperiph/16 is selected as φ T0. For details,
please refer to Fig. 5.3 System Clock Transition Diagram.
This circuit outputs the fpll clock that is quadruple of the high-speed oscillator output clock, fosc.
This lowers the oscillator input frequency while increasing the internal clock speed.
TMP19A61(rev 1.0)-5-29
TMP19A61