tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 421

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

<SIOS>
<SIOF>
<SEF>
SCK pin (output)
SI pin
INTSBI interrupt request
SBI0DBR
8-bit transmit/receive mode
Set the control register to the transfer/receive mode. Then writing the transmit data to
SBI0DBR and setting SBI0CR1 <SIOS> to "1" enables transmission and reception. The
transmit data is output through the SO pin at the falling of the serial clock, and the received
data is taken in through the SI pin at the rising of the serial clock, with the least-significant
bit (LSB) first. Once the shift register is loaded with the 8-bit data, it transfers the received
data to SBI0DBR and the INTSBI interrupt request is generated. The interrupt service
program reads the received data from the data buffer register and writes the next transmit
data. Because SBI0DBR is shared between transmit and receive operations, the received
data must be read before the next transmit data is written.
In the internal clock operation, the serial clock will be automatically in the wait state until the
received data is read and the next transmit data is written.
In the external clock mode, shift operations are executed in synchronization with the
external serial clock. Therefore, the received data must be read and the next transmit data
must be written before the next shift operation is started. The maximum data transfer rate
for the external clock operation varies depending on the maximum latency between
generating the interrupt request and reading the received data and writing the transmit
data.
At the beginning of transmission, the same value as in the last bit of the previously
transmitted data is output in a period from setting <SIOF> to "1" to the falling edge of SCK.
Transmission and reception can be terminated by clearing <SIOS> to "0" or setting
SBI0CR1 <SIOINH> to "1" in the INTSBI interrupt service program. If <SIOS> is cleared,
transmission and reception continue until the received data is fully transferred to SBI0DBR.
The program checks SBI0SR <SIOF> to determine whether transmission and reception
have come to an end. <SIOF> is cleared to "0" at the end of transmission and reception. If
<SIOINH> is set, the transmission and reception are aborted immediately and <SIOF> is
cleared to "0."
(Note) The contents of SBI0DBR will not be retained after the transfer mode is
changed. The ongoing transmission and reception must be completed by
clearing <SIOS> to "0" and the last received data must be read before the
transfer mode is changed.
Fig. 15.7.2.3 Receive Mode (Example: Internal Clock)
a
0
a
1
TMP19A61
a
2
a
3
a
4
(
rev1.0
a
5
Read the received data.
a
6
)
-15-420
a
7
a
b
0
b
1
b
<SIOS> is cleared.
2
b
3
b
4
TMP19A61
b
Read the received data.
5
b
6
b
7
b