tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 347

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Receive data
read timing
Transmit data
write timing
(INTTX0 interrupt
request)
(INTRX0 interrupt
request)
SCLK0 output
RXD0
TXD0
SCLK output mode
Send and receive (full-duplex)
The full-duplex mode is enabled by setting bit 6 <FDPX0> of the serial mode control
register 1 (SC0MOD1) to "1."
In the SCLK output mode, if SC0MOD2 <WBUF> is set to "0" and both the send and
receive double buffers are disabled, SCLK is output when the CPU writes data to the
transmit buffer. Subsequently, 8 bits of data are shifted into receive buffer 1 and the
INTRX0 receive interrupt is generated. Concurrently, 8 bits of data written to the
transmit buffer are output from the TXD0 pin, the INTTX0 send interrupt is generated
when transmission of all data bits has been completed. Then, the SCLK output stops.
In this, the next round of data transmission and reception starts when the data is read
from the receive buffer and the next send data is written to the transmit buffer by the
CPU. The order of reading the receive buffer and writing to the transmit buffer can be
freely determined. Data transmission is resumed only when both conditions are
satisfied.
If SC0MOD2 <WBUF> = "1" and double buffering is enabled for both transmission and
reception, SCLK is output when the CPU writes data to the transmit buffer.
Subsequently, 8 bits of data are shifted into receive buffer 1, moved to receive buffer 2,
and the INTRX0 interrupt is generated. While 8 bits of data is received, 8 bits of
transmit data is output from the TXD0 pin. When all data bits are sent out, the INTTX0
interrupt is generated and the next data is moved from the transmit buffer 2 to transmit
buffer 1. If transmit buffer 2 has no data to be moved to transmit buffer 1 (SC0MOD2
<TBEMP> = 1) or when receive buffer 2 is full (SC0MOD2 <RBFULL> = 1), the SCLK
output is stopped. When both conditions are satisfied, i.e., receive data is read and
send data is written, the SCLK output is resumed and the next round of data
transmission is started.
bit 0
bit 0
<WBUF> = "0" (if double buffering is disabled)
TMP19A61 (rev1.0)-13-346
bit 1
bit 1
bit 5
bit 5
bit 6
bit 6
bit 7
bit 7
TMP19A61
bit 0
bit 0
bit 1
bit 1