tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 292
tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
TMP19A61F10XBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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Programming example:
Main
programming
INT0 での設定
INTTBxx での設定
TBxxCR
TBxxMOD
TBxxFFCR
PxCR
PxFC1
IMC1
IMC5
TBxxRUN
TBxxRG0L
TBxxRG0H
TBxxRG1L
TBxxRG1H
TBxxFFCR
IMC5
TBxxFFCR
IMC5
If a delay is not required, TBxxFF0 is reversed when data is taken into TBxxCP0H/L, and
TBxxRG1L/H is set to the sum of the TBxxCP0H/L value (c) and the one-shot pulse width
(p), (c + p), by generating the INT5 interrupt. TB5FF0 is enabled to reverse when UC0
matches with TBxxRG1L/H, and is disabled by generating the INTTBxx interrupt.
TBxxIN0 pin with a 3-ms delay
X; Don't care ⎯;no change
←
← X
← X
←
←
← X
← X
←
←
←
←
←
← X
← X
← X
← X
7
1
−
−
X
X
X
X
X
X
−
X
X
X
X
X
X
*
*
*
*
6
0
X
X
−
−
−
1
−
−
1
−
−
−
0
X
1
−
−
−
X
1
−
−
−
*
*
*
*
5
X
1
0
−
−
−
1
−
−
1
−
−
−
0
−
1
−
−
−
−
1
−
−
−
*
*
*
*
Output a 2-ms one-shot pulse triggered by an external pulse from the
4
X
0
0
−
−
0
0
0
0
0
0
0
0
0
−
0
0
0
0
−
0
0
0
0
* Clock conditions
*
*
*
*
TMP19A61 (rev 1.0)11-291
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
3
1
0
−
−
−
1
0
*
*
*
*
X
2
0
0
1
1
−
1
−
−
0
−
−
−
1
1
1
−
−
−
0
0
−
−
−
*
*
*
*
X
X
1
0
1
−
−
−
0
−
−
0
−
−
−
−
0
−
−
−
−
0
−
−
−
*
*
*
*
X
0
1
0
−
−
−
0
−
−
0
−
−
−
1
−
0
−
−
−
−
0
−
−
−
*
*
*
*
System clock
High-speed clock gear : 1X (fc)
Prescaler clock
Start the TMRBxx module.
Puts to a free-running state. Uses φT1 for counting.
Takes data into TBxxCP0 at the rising of TBxxIN0 input
Clears TBxxFF0 to zero.
Disables TBxxFF0 to reverse.
Assigns Px2 pin to TBxxOUT.
Enables INT5.
These are 32-bit registers and must be all processed.
Disables INTTBxx.
These are 32-bit registers and must be all processed.
Starts TMRBxx.
TBxxCP0 + 3ms/φT1
TBxxRG0 + 2ms/φT1
Enables TBxxFF0 to reverse when there is a match with
TBxxRG0, 1.
Enables INTTBxx.
Disables TBxxFF0 to reverse when there is a match with
TBxxRG0, 1
Disables INTTBxx.
: High speed (fc)
: fperiph/4 (fperiph
TMP19A61
fsys)
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