tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 305

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TMP19A61
12.2.6
32-bit Compare Register
This is a 32-bit register for specifying a compare value. TMRC has two built-in compare
registers, CMPA0 and CMPA1. If values set in these compare registers match the value of
TBTA, the match detection signal of a comparator becomes active. "Compare enable" or
"compare
disable"
can
be
specified
with
the
compare
control
register
CMPCTL<CMPEN1:0>.
To set TCCMPn to a specific value, data must be transferred to TCCMPn in the order of
lower to higher bits by using a byte data transfer instruction four times.
CMPAn forms a pair with a register buffer "n." "Enable" or "disable" of the double buffers is
controlled by the compare control register CMPCTL <CMPRDEn>. If <CMPRDEn> is set to
"0," the double buffers are disabled. If <CMPRDEn> is set to "1," they are enabled.
If the double buffers are enabled, data transfer from the register buffer "n" to the compare
register CMPAn takes place when the value of TBTA matches that of CMPAn.
Because CMPAn is indeterminate when a reset is performed, it is necessary to prepare and
write data in advance. A reset initializes CMPACTL <CMPRDEn> to "0" and disables the
double buffers. To use the double buffers, data must be written to the compare register, <
CMPRDEn > must be set to "1," and then the following data must be written to the register
buffer.
CMPAn and the register buffer are assigned to the same address. If < CMPRDEn > is "0,"
the same value is written to CMPAn and each register buffer. If <CMPRDEn> is "1," data is
written to each register buffer only. Therefore, to write an initial value to the compare
register, it is necessary to set the double buffers to "disable."
(n=0, 1)
TMP19A61 (rev1.0)-12-304