tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 527
tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
Available stocks
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Part Number
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Quantity
Price
Part Number:
TMP19A61F10XBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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Address
Normal
comman
ds
Block
erase
Auto
page
progra
mming
ID-REA
D
Protecti
on
progra
mming
Protecti
on
erase
(Note)
(Note)
(Note)
bit
bit
Flash area
Flash area
Flash area
Flash area
Flash area
Flash area
[31:21]
Address setting can be performed according to the "Normal bus write cycle address
configuration" from the first bus cycle.
Table 22.17 "Flash Memory Access from the Internal CPU" can also be used.
"0" is recommended" can be changed as necessary.
Addr
(5)
PBA: Protection bit address (Set the seventh bus write cycle address for protection bit programming)
PA: Program page address (Set the fourth bus write cycle address for page programming operation)
PBA: Protection bit address (Set the seventh bus write cycle address for protection bit erasure)
“0”
recom
mende
d.
“0”
recom
mend
ed.
“0”
recom
mend
ed.
“0”
recom
mend
ed.
mende
recom
recom
mend
“0” is
“0” is
Addr
[20]
ed.
Address bit configuration for bus write cycles
BA: Block address (Set the sixth bus write cycle address for block erase operation)
d.
is
is
is
is
IA: ID address (Set the fourth bus write cycle address for ID-Read operation)
xed to “0”. ” is recommended.
Table 22. 8 Address Bit Configuration for Bus Write Cycles
xed to“0”
Chip
selecti
on
Chip
selecti
on
Chip
selecti
on
selecti
Addr
Chip
[19]
on
“0” is
recommended.
Block
selection
Block
selection
[18:17]
recommended.
recommended.
Addr
Normal bus write cycle address configuration
“0” is
“0” is
TMP19A61 (rev1.0) 22-526
Addr
[16]
Protection bit write
“00”: Block 0
“01”: Block 1
“10”: Block 2
“11”: Block 3
Erase
protection for
0: Block 0,1
1: Block 2,3
Addr
[15]
ID address
Page selection
Addr
[14]
Command
Others: 0 (recommended)
Addr [1:0]=0 (fixed),
Addr
[13]
Others: 0 (recommended)
Addr [1:0]=0 (fixed),
[12:9]
Addr
Others: 0 (recommended)
Others: 0 (recommended)
Addr [1:0]=0 (fixed),
Addr [1:0]=0 (fixed),
TMP19A61
Addr [1:0]=0 (fixed),
Others: 0 (recommended)
Addr
[8]
Addr [1:0]=0 (fixed),
Others: 0
(recommended)
[7:0]
Addr
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