tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 60

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.9.2
6.9.2.1
This section describes detailed operation of interrupt processing using the basic flow chart of Fig. 6.4.
After interrupt request arbitration, INTC sets the interrupt vector and interrupt level of the interrupt
request accepted to IVR and ILEV<CMASK>, respectively, to notify the TX19A processor core of the
interrupt level. When the interrupt level is notified, the TX19A processor core sets Status <EXL> of the
CP0 register to "1" to disable interrupts and saves the PC value at the interrupt generation to EPC. If the
shadow register set is enabled (CP0 register SSCR <SSD> = 0), the processor core sets the interrupt
level to SSCR <CSS> of the CP0 register and switches the register bank.
When an interrupt is accepted, any ongoing execution is suspended and it automatically jumps to the
exception vector address (for interrupts). Fig. 6.5 shows the sequence of accepting interrupts.
Interrupt Processing
Interrupt Response and Return
Hardware processes to accept interrupts
･ Cause<BD> ← 1
･ EPC ← Set the PC of Jump or
Branch instruction to EPC
Fig. 6.5 Hardware Process Flow to Accept Interrupts
Cause< ExcCode>
Status<EXL>
SSCR<CSS>
YES
Jump to exception vector address
TMP19A61(rev1.0)-6-59
Cause<IV>=0
Cause<IV>=1
PC ← 0xBFC0_0380
PC ← 0xBFC0_0400
Interrupt detection
The highest priority
ILEV <CMASK>,
Both Status<EXL>
and <ERL> are 0?
Higher
interrupt level is
interrupt request?
YES
YES
Within branch
Compared to
delay slot？
Status<EI>?
1
← 0x00
← 1
←Interrupt level
･ Cause<BD> ← 0
･ EPC ← PC
Lower
NO
NO
NO
0
Interrupt suspended
TMP19A61