tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 418

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

15.7.2
Transfer Modes
INTSBI interrupt
The transmit mode, the receive mode or the transmit/receive mode can be selected by
programming SBI0CR1 <SIOM1:0>.
Set the control register to the transmit mode and write the transmit data to SBI0DBR.
After writing the transmit data, writing "1" to SBI0CR1 <SIOS> starts the transmission.
The transmit data is moved from SBI0DBR to a shift register and output to the SO pin,
with the least-significant bit (LSB) first, in synchronization with the serial clock. Once the
transmit data is transferred to the shift register, SBI0DBR becomes empty, and the
INTSBI (buffer-empty) interrupt is generated, requesting the next transmit data.
In the internal clock mode, the serial clock will be stopped and automatically enter the
wait state, if next data is not loaded after the 8-bit data has been fully transmitted. The
wait state will be cleared when SBI0DBR is loaded with the next transmit data.
In the external clock mode, SBI0DBR must be loaded with data before the next data shift
operation is started. Therefore, the data transfer rate varies depending on the maximum
latency between when the interrupt request is generated and when SBI0DBR is loaded
with data in the interrupt service program.
At the beginning of transmission, the same value as in the last bit of the previously
transmitted data is output in a period from setting SBI0SR <SIOF> to "1" to the falling
edge of SCK.
Transmission can be terminated by clearing <SIOS> to "0" or setting <SIOINH> to "1" in
the INTSBI interrupt service program. If <SIOS> is cleared, remaining data is output
before transmission ends. The program checks SBI0SR <SIOF> to determine whether
transmission has come to an end. <SIOF> is cleared to "0" at the end of transmission. If
<SIOINH> is set to "1," the transmission is aborted immediately and <SIOF> is cleared
to "0."
In the external clock mode, <SIOS> must be set to "0" before the next transmit data shift
operation is started. Otherwise, operation will stop after dummy data is transmitted.
SBI0CR1 ← 0 1 0 0 0 X X X
SBI0DBR ← X X X X X X X X
SBI0CR1 ← 1 0 0 0 0 X X X
SBI0DBR ← X X X X X X X X
8-bit transmit mode
7 6 5 4 3 2 1 0
TMP19A61
(
rev1.0
Selects the transmit mode.
Writes the transmit data.
Starts transmission.
Writes the transmit data.
)
-15-417
TMP19A61