tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 214

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2 waits automatically inserted
2 waits automatically inserted + 2N (N=1)
3 waits automatically inserted + 2N (N=1)
2 waits automatically inserted + 2N (N=2)
0 wait
Fig. 8.14 shows the write operation timing when 0 wait, waits automatically inserted, and waits
automatically inserted + external waits are inserted in the multiplexed bus mode.
fsys
A[23:16]
AD[15:0]
A[23:16]
AD[15:0]
A[23:16]
AD[15:0]
A[23:16]
AD[15:0]
A[23:16]
AD[15:0]
/WAIT
/WAIT
/WAIT
/WAIT
/WAIT
ALE
/WR
ALE
/WR
ALE
/WR
ALE
/WR
ALE
/WR
--- External wait sampling point
External wait sampling points take place before a cycle of waits automatically
inserted is finished and before a 2N_wait cycle is finished as shown above.
The same applies to combinations of other numbers of waits.
Fig. 8.14 Write Operation Timing Diagram
Lower-order address
Lower-order address
Lower-order address
Lower-order address
Lower-order address
TMP19A61(rev1.0)-8-213
tsys
2 waits automatically
2 waits automatically
2 waits automatically
Hi h
Higher-order address
Higher-order address
Higher-order address
Higher-order address
2 waits automatically
inserted
inserted
inserted
d
inserted
dd
2N_WAIT
Data
Data
Data
Data
Data
2N_WAIT
2N WAIT
TMP19A61