tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 331

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3. Framing error <FERR>: Bit 2 of the SC0CR register
In the UART mode, this bit is set to "1" when a framing error is generated. This flag is
set to "0" when it is read. A framing error is generated if the corresponding stop bit is
determined to be "0" by sampling the bit at around the center. Regardless of the
<SBLEN> (stop bit length) setting of the serial mode control register 2, SC0MOD2, the
stop bit status is determined by only 1 bit on the receive side.
Operation mode
UART
I/O interface
(SCLK input)
I/O interface
(SCLK output)
TMP19A61 (rev1.0)-13-330
Error flag
OERR
PERR
FERR
OERR
PERR
FERR
OERR
PERR
FERR
Function
Overrun error flag
Parity error flag
Framing error flag
Overrun error flag
Underrun error flag （ WBUF ＝ 1 ）
Fixed to 0 （ WBUF ＝ 0 ）
Fixed to 0
Operation undefined
Operation undefined
Fixed to 0
TMP19A61