tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 283

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TBnMOD
(0xFFFF_Fxx2)
<TBnCLK1:0>: Selects the TMRBn timer count clock.
<TBnCLE>: Clears and controls the TMRBn up-counter.
<TBnCPM1:0>: Specifies TMRBn capture timing.
<TBnCP0>: Captures count values by software and takes them into capture register 0 (TBnCP0).
“0” :
“1” :
“00” :
“01”: Takes count values into capture register 0 (TBnCP0) upon the rising of TBnIN0 pin input.
Takes count values into capture register 1 (TBnCP1) upon the rising of TBnIN1 pin input.
“10”: Takes count values into capture register 0 (TBnCP0) upon the rising of TBnIN0 pin input.
“11”: Takes count values into capture register 0 (TBnCP0) upon the rising of timer output for capture
trigger (CAPTRG) and into capture register 1 (TBnCP1) upon the falling of CAPTRG (CAPTRG for
TMRB08 ~ 0F: TB1OUT, for TMRB10 ~ 13: TB2OUT).
Takes count values into capture register 1 (TBnCP1) upon the falling of TBnIN0 pin input.
Bit symbol
Read/Write
After reset
Function
Disables clearing of the up-counter.
Clears up-counter if there is a match with timer register 1 (TBnRG1).
Capture disable
This can be read as “0”.
7
R
0
6
TMP19A61 (rev 1.0)11-282
Capture
control by
software
0: Capture
by software
1: Don't care
TBnCP0
TMRBn mode register
W
5
1
00: Disable
01: TBnIN0 ↑ TBnIN1 ↑
10: TBnIN0 ↑ TBnIN0 ↓
11: CAPTRG ↑ CAPTRG ↓
Capture timing
TBnCPM1 TBnCPM0
4
0
3
0
1:Clear/
Up-counter
control
0: Clear/
disable
TBnCLE
enable
R/W
2
0
Selects source clock
00: TBnIN0 pin input
01: φT1
10: φT4
11: φT16
TBnCLK1
1
TMP19A61
0
TBnCLK0
0
0