tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 385

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Receive data
write timing
Receive data
write timing
Receive data
write timing
(HINTRX0 interrupt request)
(HINTRX0 interrupt request)
(HINTRX interrupt request)
RBFULL
RBFULL
HSCLK0 output
HSCLK0 output
HSCLK0 output
HRXD0
HRXD0
HRXD0
<WBUF> ＝ ”1”( if double buffering is enabled and data cannot be read from buffer 2)
Fig. 14-23 Receive Operation in the I/O Interface Mode (HSCLK0 Output Mode)
<WBUF> ＝ ”1”( if double buffering is enabled and data is read from buffer 2)
HSCLK output mode
Receiving data
bit
bit
In the HSCLK output mode, if HSC0MOD2 <WBUF> = "0" and receive double
buffering is disabled, a synchronous clock pulse is output from the HSCLK0 pin and
the next data is shifted into Receive Buffer 1 each time the CPU reads received data.
When all the 8 bits are received, the HINTRX0 interrupt is generated.
The first HSCLK output can be started by setting the receive enable bit HSC0MOD0
<RXE> to "1." If the receive double buffering is enabled with HSC0MOD2 <WBUF> set
to "1," the first frame received is moved to Receive Buffer 2 and Receive Buffer 1 can
receive the next frame successively. As data is moved from Receive Buffer 1 to
Receive Buffer 2, the receive buffer full flag HSC0MOD2 <RBFULL> is set to "1" and
the HINTRX0 interrupt is generated.
While data is in Receive Buffer 2, if CPU/DMAC cannot read data from Receive Buffer
2 in time before completing reception of the next 8 bits, the HINTRX0 interrupt is not
generated and the HSCLK0 clock stops. In this state, reading data from Receive Buffer
2 allows data in Receive Buffer 1 to move to Receive Buffer 2 and thus the HINTRX0
interrupt is generated and data reception resumes.
7
7
<WBUF> ＝ ”0”( if double buffering is disabled)
bit 0
bit 0
bit 0
TMP19A61(rev. 1.0) 14-384
bit 1
bit 1
bit 1
bit 6
bit 6
bit 6
bit 7
bit 7
bit 7
TMP19A61
bit 0
bit 0