tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 386

no-image

tmp19a61f10xbg

Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMP19A61F10XBG
Manufacturer:
TOSHIBA
Quantity:
1 000
Part Number:
TMP19A61F10XBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
(Note) To receive data, HSC0MOD <RXE> must always be set to "1" (receive enable)
Receive data
read timing
HSCLK0 input
(<SCLKS>=0
Rising edge mode)
HSCLK0 input
(<SCLKS>=1
Falling edge mode)
Receive data
write timing
HSCLK0 input
(<SCLKS>=0
Rising edge mode)
HSCLK0 input
(<SCLKS>=1
Falling edge mode)
(HNTRX0 interrupt request)
(HINTRX0 interrupt request)
HSCLK input mode
RBFULL
RBFULL
OERR
HRXD0
HRXD0
regardless of the HSCLK input or output mode.
Fig. 14-24 Receive Operation in the I/O Interface Mode (HSCLK0 Input Mode)
In the HSCLK input mode, since receive double buffering is always enabled, the
received frame can be moved to Receive Buffer 2 and Receive Buffer 1 can receive
the next frame successively.
The HINTRX0 receive interrupt is generated each time received data is moved to
Received Buffer 2.
bit 0
bit 0
If data is read from buffer 2
If data cannot be read from buffer 2
TMP19A61(rev 1.0)14-385
bit 1
bit 1
bit 5
bit 5
bit 6
bit 6
bit 7
bit 7
TMP19A61
bit 0
bit 0

Related parts for tmp19a61f10xbg