tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 497

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

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Test-Logic-Reset
If the TAP controller is in a reset state, the device identification register is selected by default.
The most significant bit in the boundary scan register is cleared to "0," and the output is disabled.
The TAP controller remains in the Test-Logic-Reset state if TMS is "1." If "0" is input into TMS in
the Test-Logic-Reset state, the TAP controller goes into the Run-Test/Idle state.
Run-Test/Idle
In the Run-Test/Idle state, the IC goes into test mode only if a specific instruction, such as the
built-in self test (BIST) instruction, is issued. If an instruction that cannot be executed in the
Run-Test/Idle state has been issued, the test data register selected by the last instruction
maintains the existing state.
The TAP controller remains in the Run-Test/Idle state if TMS is "0." If "1" is input into TMS, the
TAP controller goes into the Select-DR-Scan state.
Select-DR-Scan
The Select-DR-Scan state of the TAP controller is a transient state. In this state, the IC performs
no operations. If "0" is input into TMS when the TAP controller is in the Select-DR-Scan state, the
TAP controller goes into the Capture-DR state. If "1" is input into TMS, the instruction column
goes into the Select-IR-Scan state.
Select-IR-Scan
The Select-IR-Scan state of the TAP controller is a transient state. In this state, the IC performs
no operations.
If "0" is input into TMS when the TAP controller is in the Select-IR-Scan state, the TAP controller
goes into the Capture-IR state. If "1" is input into TMS, the TAP controller returns to the
Test-Logic-Reset state.
Capture-DR
If the data register selected by the instruction register has parallel inputs when the TAP controller
is in the Capture-DR state, data is loaded into the data register in a parallel fashion. If the data
register does not have parallel inputs or if data does not need to be loaded into the selected test
data register, the data register maintains the existing state.
If "0" is input into TMS when the TAP controller is in the Capture-DR state, the TAP controller
goes into the Shift-DR state. If "1" is input into TMS, the TAP controller goes into the Exit 1-DR
state.
The TAP controller operates in each state described below. In Fig. 21.7, a column to the left is
the data column and a column to the right is the instruction column. The data column represents
the data register (DR), and the instruction column represents the instruction register (IR).
TMP19A61 (rev1.0)21-496
TMP19A61