tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 98

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

7.3
The port 1 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in
units of bits. Output can be set by using the control register P1CR and the function registers P1FC1 and P1FC2.
A reset allows all bits of the output latch P1, P1CR, P1FC1 and P1FC2 to be cleared to "0" and the port 1 to be
put in output disable mode.
Besides the general-purpose input/output function, the port 1 performs other functions: D8 through D15
function as a data bus, AD8 through AD15 function as an address data bus, and A8 through A15 function as an
address bus. To access external memory, registers P1CR, P1FC1 and P1FC2 must be provisioned to allow the
port 1 to function as either an address bus or an address data bus.
If the BUSMD pin is set to "L" level during a reset, the port 1 is put in separate bus mode (D8 to D15). If it is set
to "H" level during a reset, the port 1 is put in multiplexed mode (AD8 to AD15 or A8 to A15).
Port 1 (P10~P17)
AD8~AD15
(Output latch)
(Function
(Function
(direction
P1FC1
P1FC2
P1CR
control)
control)
control)
P1 read
P1
STOP/ RESET
drive disable
AD8~AD15
D8~D15
External bus
TMP19A61(rev1.0) 7-97
Fig. 7.2 Port 1 (P10~P17)
openinig
1
0
Address/ data
output enable
A8~A15
1
0
1
1
0
0
P1 access
External read
TMP19A61
Port 1
P10~P17
(D8~D15)
(AD8~AD15/A8~A15)
RESET