tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 387

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

In the HSCLK output mode, if HSC0MOD2 <WBUF> is set to "0" and both the transmit and
receive double buffers are disabled, HSCLK is output when the CPU writes data to the
transmit buffer. Subsequently, 8 bits of data are shifted into Receive Buffer 1 and the
HINTRX0 receive interrupt is generated. Concurrently, 8 bits of data written to the transmit
buffer are output from the HTXD0 pin, the HINTTX0 transmit interrupt is generated when
transmission of all data bits has been completed. Then, the HSCLK output stops. In this,
the next round of data transmission and reception starts when the data is read from the
receive buffer and the next transmit data is written to the transmit buffer by the CPU. The
order of reading the receive buffer and writing to the transmit buffer can be freely
determined. Data transmission is resumed only when both conditions are satisfied.
If HSC0MOD2 <WBUF> = "1" and double buffering is enabled for both transmission and
reception, HSCLK is output when the CPU writes data to the transmit buffer. Subsequently,
8 bits of data are shifted into Receive Buffer 1, moved to Receive Buffer 2, and the
HINTRX0 interrupt is generated. While 8 bits of data is received, 8 bits of transmit data is
output from the HTXD0 pin. When all data bits are sent out, the HINTTX0 interrupt is
generated and the next data is moved from the Transmit Buffer 2 to Transmit Buffer 1. If
Transmit Buffer 2 has no data to be moved to Transmit Buffer 1 (HSC0MOD2 <TBEMP> =
1) or when Receive Buffer 2 is full (HSC0MOD2 <RBFULL> = 1), the HSCLK output is
stopped. When both conditions are satisfied, i.e., receive data is read and transmit data is
written, the HSCLK output is resumed and the next round of data transmission is started.
Transmit and receive (full-duplex)
The full-duplex mode is enabled by setting bit 6 <FDPX0> of the serial mode control
register 1 (HSC0MOD1) to "1".
HSCLK output mode
TMP19A61(rev. 1.0) 14-386
TMP19A61