tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 3

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(7) General-purpose serial interface: 9 channels
(8) Serial bus interface: 2 channels
(9) High-speed serial bus interface: 2 channels
(6)32-bit timer
(5)16-bit timer
(3) External memory expansion
2) Both high performance and low power consumption have been achieved.
•High performance
•Low power consumption
3) High-speed interrupt response suitable for real-time control
(2) Internal program memory and data memory
(4) DMA controller
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TMP19A61CDXBG
TMP19A61C10XBG
TMP19A61F10XBG
Almost all instructions can be executed with one clock.
High performance is possible via a three-operand operation instruction.
5-stage pipeline
Built-in high-speed memory
DSP function: A 32-bit multiplication and accumulation operation can be executed with one
clock.
Optimized design using a low power consumption library
Standby function that stops the operation of the processor core
Independency of the entry address
Automatic generation of factor-specific vector addresses
Automatic update of interrupt mask levels
ROM correction function: 8word×12 block
Expandable to 16 megabytes (for both programs and data)
External data bus:
Activated by an interrupt or software
Data to be transferred to internal memory, internal I/O, external memory, and external I/O
16-bit interval timer mode
16-bit event counter mode
16-bit PPG output
Input capture function
2-phase pulse input counter function (2 channels assigned to perform this function):
32-bit input capture register: 4 channels
32-bit compare register: 4 channels
32-bit time base timer: 2 channels
Selectable between the UART mode and the synchronization mode
Selectable between I
Selectable between UART mode/ the high-speed synchronization mode
(Max: 10Mbps fsys=40MHz)
Product name
Separate bus/multiplexed bus
Chip select/wait controller : 4 channels
Added CS recovery function (wait is inserted within RD (WR)↑−CS↑)
(For 1 clock)
External wait X+2N-capable（X=2 to 15）
Changed ALE width (1-4 clocks)
2
1Mbyte(Flash)
Built-in ROM
C bus mode/ the clock synchronization mode
TMP19A61(rev 1.0)-1-2
512Kbyte
: 36 channels
1Mbyte
: Coexistence of 8- and 16-bit widths is possible.
Built-in RAM
40Kbyte
48Kbyte
48Kbyte
: 8 channels
TMP19A61