tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 56

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.9.1.2
(1)
external pins
(2) Two-phase
counter interrupts
(3) Other interrupts
(Note 1) In level detection, the value is checked at internal clock timing each time. Edge detection is made by
(Note 2) In interrupt initialization, follow the order of the interrupt detection route as indicated in Table 6.4
Interrupts
INT0~INTB
Interrupt
The registers to be set in using different interrupt factors are as listed below:
before enabling the interrupts with the CP0 register. If any different setting order is used, an
unexpected interrupt may be generated. So, be sure to clear interrupt factors before setting interrupt
permission. Similarly, if interrupts are to be disabled, first disable the interrupt by the CP0 register and
then set the registers accordingly in the reverse order of interrupt detection.
comparing the previous value with the current value at internal clock timing. As for CG edge detection,
the edge of the input signal is detected without using internal clock.
Initialization for Individual Interrupt Factors
from
INTC
INTC
INTC
Detected
CG
at
Table 6.5 Registers to be Set for Detecting Interrupts
Registers to be
PxFC(PORT)
PxCR(PORT)
IMCxx(INTC)
PxFC(PORT)
PxCR(PORT)
IMCGx(CG)
IMCxx(INTC)
PxFC(PORT)
PxCR(PORT)
IMCxx(INTC)
IMCxx(INTC)
Set
TMP19A61(rev1.0)-6-55
With INTC, "L" and "H" levels and falling and rising
edges can be set.
If it is to be used for recovery from Standby mode, it
must be set to "H" with INTC. With CG, "L" and "H"
levels and falling/rising edges can be set.
It must be set to rising edge with INTC.
With INTC, "L" and "H" levels and falling and rising
edges can be set.
Interrupt detection levels available (setting in active
condition)
TMP19A61