tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 342

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

13.5
13.5.1
TBRUN
Transmit data
write timing
Transmit data
write timing
(INTTX0 interrupt request)
(INTTX0 interrupt
request)
SCLK0 output
SCLK0 output
Operation in Each Mode
Mode 0 (I/O interface mode)
TBRUN
TBEMP
TXD0
TXD0
<WBUF> ＝ "1" (if double buffering is enabled) (if there is data in buffer 2)
Mode 0 consists of two modes, i.e., the "SCLK output" mode to output synchronous clock
and the "SCLK input" mode to accept synchronous clock from an external source. The
following operational descriptions are for the case use of FIFO is disabled. For details of
FIFO operation, refer to the previous sections describing receive/transmit FIFO functions.
SCLK output mode
Sending data
In the SCLK output mode, if SC0MOD2<WBUF> is set to "0" and the transmit double
buffers are disabled, 8 bits of data are output from the TXD0 pin and the synchronous
clock is output from the SCLK0 pin each time the CPU writes data to the transmit buffer.
When all data is output, the INTTX0 interrupt is generated.
If SC0MOD2 <WBUF> is set to "1" and the transmit double buffers are enabled, data is
moved from transmit buffer 2 to transmit buffer 1 when the CPU writes data to transmit
buffer 2 while data transmission is halted or when data transmission from transmit
buffer 1 (shift register) is completed. When data is moved from transmit buffer 2 to
transmit buffer 1, the transmit buffer empty flag SC0MOD2 <TBEMP> is set to "1," and
the INTTX0 interrupt is generated. If transmit buffer 2 has no data to be moved to
transmit buffer 1, the INTTX0 interrupt is not generated and the SCLK0 output stops.
<WBUF> ＝ "0" (if double buffering is disabled)
bit 0
bit 0
TMP19A61 (rev1.0)-13-341
bit 1
bit 1
bit 6
bit 6
bit 7
bit 7
TMP19A61
bit 0
bit 0