tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 64
tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
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6.9.3.1
Interrupts can be enabled by setting Status <IE> of the CP0 register to "1" while Status <EXL> is set to
"0." This optional setting is made by the software program when it is necessary.
When an interrupt is generated, Status <EXL> of the CP0 register is set to "1" disabling further interrupts.
This process is automatically performed by hardware.
If multiple interrupts are to be enabled, it is necessary to set Status <EXL> of the CP0 register to "0" to
enable interrupts after relevant registers are saved. If interrupts are enabled before saving registers, a
higher priority level interrupt could corrupt the register data. This optional setting is made by the
software program when it is necessary.
This is the period multiple interrupts are enabled. Interrupts with a level higher than the present interrupt
level (ILEV <CMASK>) are to be accepted. If it is desired to disable interrupts during this period, set
Status <IE> of the CP0 register to "0."
If multiple interrupts are enabled, it is necessary to set Status <EXL> of the CP0 register to "1" to disable
interrupts before returning relevant register values. If registers are saved before disabling interrupts, a
higher priority level interrupt could corrupt the register data. This optional setting is made by the
software program when it is necessary.
This instruction returns the system to the state before the interrupt generation. If this instruction is
executed while Status <EXL> of the CP0 register is set to "1," the Status <EXL> will be automatically set
to "0" and interrupt is enabled (provided that Status <IE> of the CP0 register is set to "1").
Interrupts can be disabled by setting Status <IE> of the CP0 register to "0." This optional setting is made
by the software program when it is necessary.
① Status<IE>=1
② Interrupt generation
③ Status<EXL>=0
④ Multiple interrupts enabled
⑤ Status<EXL>=1
⑥ ERET instruction
⑦ Status<IE>=0
Interrupt Control for Multiple Interrupts
Fig. 6.6 Interrupt Enable/Disable Control Sequence for Multiple Interrupts
TMP19A61(rev1.0)-6-63
TMP19A61
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