tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 341

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(0xFFFF_F70A)
(0xFFFF_F70B)
(0xFFFF_F707)
SC0RST
SC0TST
SC0EN
<SIOE>: It specifies SIO operation. When SIO operation is disabled, the clock will not be
(Note)
(Note)
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
supplied to the SIO module except for the register part and thus power consumption
can be reduced (other registers cannot be accessed for read/write operation). When
SIO is to be used, be sure to enable SIO by setting "1" to this register before setting
any other registers of the SIO module. If SIO is enabled once and then disabled, any
register setting is maintained.
Function
Function
Function
The <ROR> bit is cleared to "0" when receive data is read from the SC0BUF
register.
The <TUR> bit is cleared to "0" when transmit data is written to the SC0BUF
register.
RX FIFO
Overrun
TX FIFO
Under run
1:
Generated
1:
Generated
ROR
TUR
R
R
7
0
7
1
7
0
Fig. 13.4.11 Transmit FIFO Status Register
Fig. 13.4.10 Receive FIFO Status Register
Fig. 13.4.12 SIO Enable Register
TMP19A61 (rev1.0)-13-340
6
6
6
0
0
0
5
5
5
0
0
0
R
R
4
4
4
R
0
0
0
3
3
3
0
0
0
Status of RX FIFO fill level
000: Empty
001: 1Byte
010: 2Bytes
011: 3Byte s
Status of TX FIFO fill level
000: Empty
001: 1Byte
010: 2Bytes
011: 3Byte s
100: 4Bytes
100: 4Bytes
RLVL2
TLVL2
2
2
2
0
0
0
TMP19A61
RLVL1
TLVL1
１
1
R
R
1
0
0
0
SIO
operation
0: Disable
1: Enable
RLVL0
TLVL0
SIOE
R/W
0
0
0
0
0
0