tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 93

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.12
6.12.1
The following paragraphs describe some points to be kept in mind in using interrupts. User programs
must be written in a manner to satisfy the following details.
Cautions in Using Interrupts
Cautions Related to TX19A Processor Core
・ Exceptions cannot be disabled. Note that there are some cases where two different
・ Software interrupts are different from the "software set" to be used as one of hardware
・ Immediately after overwriting SSCR of the CP0 register, add two NOP instructions to
・ In case multiple interrupts of the same interrupt level are accepted by changing ILEV
・ Only 32-bit ISA access can be used to access IER of the CP0 register.
・ Different stack pointers (r29) are used for Shadow Register Set number 0 and Shadow
・ If an ERET instruction is executed while interrupts are disabled by setting Status <ERL>
・ Don't execute an ERET instruction within two clock cycles after accessing Status,
・ If Status <ERL/EXL/IE> of the CP0 register is set to disable interrupts, interrupts are
・ If Status <ERL/EXL/IE> of the CP0 register is set to enable interrupts, interrupts are
instructions can be distinguished only by exception generation. So, properly use them
according to the specific usage.
interrupt factors.
allow for register bank switching as it takes two clock cycles.
<CMASK>, the register bank will not be switched. The users need to program an
additional process for saving the contents of the register.
Register Set numbers 1 to 7; it is necessary to set them separately (twice). If it is desired
to use a common stack pointer, you can do so by setting SSCR<CSS> to "1" in the main
process to use Shadow Register Set number 1. In this case, when a level 1 interrupt is
accepted, the register bank will not be switched. The users need to program an
additional process for saving the contents of the register..
of the CP0 register to "1," it returns to the main process by using ErrorEPC of the CP0
register as the return address. As the TX19A processor core saves the interrupt return
address to EPC, you should be careful if Status <ERL> is to be used for disabling
interrupts.
ErrorEPC, EPC, or SSCR of the CP0 register.
disabled at the time of instruction execution (E stage) but any value set to the register is
reflected only two clocks later.
enabled two clocks after the instruction execution (E stage); any value set to the register
is also reflected two clocks after the instruction execution (E stage).
TMP19A61(rev1.0)-6-92
TMP19A61