tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 378

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

LITTLE
BIG
<RXTXCNT>:0 The function to automatically disable RXE/TXE bits is disabled.
<RFIE>: When RX FIFO is enabled, receive interrupts are enabled or disabled by this parameter.
<TFIE>: When TX FIFO is enabled, transmit interrupts are enabled or disabled by this parameter.
<RFST>: When RX FIFO is enabled, the number of RX FIFO bytes to be used is selected.
<CNFG>: If enabled, the HSCOMOD1 <FDPX1:0> setting automatically configures FIFO as follows:
(0xFFFF_E80C)
(0xFFFF_E80F)
HSC0FCNF
(Note) Regarding TX FIFO, the maximum number of bytes being configured is always available.
<FDPX1:0> = 11 (Full duplex) ----------- When either of the above two conditions is satisfied, TXE/RXE
Note:
<FDPX1:0>=01 (Half duplex RX) ---- 4-byte RX FIFO
<FDPX1:0>=10 (Half duplex TX) ---- 4-byte TX FIFO
<FDPX1:0>=11 (Full duplex) ---- 2-Byte RX FIFO + 2-Byte TX FIFO
<FDPX1:0> = 01 (Half duplex RX) ------When the RX FIFO is filled up with the specified number of valid
<FDPX1:0> = 10 (Half duplex TX) ------When the TX FIFO is empty, TXE is automatically set to "0" to
(0xFFFF_E800)
The available number of bytes is the bytes already written to the TX FIFO.
HSC0BUF works as a transmit buffer for WR operation and as a receive buffer
for RD operation.
HSC0BUF
Bit symbol
Read/Write
After reset
Function
Be sure to write "000."
The registers must be byte accessed in setting them.
Reserved
0: The maximum number of bytes of the FIFO configured 4 bytes when
<FDPX1:0> = 01 (Half duplex RX) and 2 bytes for <FDPX1:0> = 11 (Full duplex
1: Same as the fill level for receive interrupt generation specified by HSC0RFC
<RIL1:0>
RB7
TB7
7
7
7
0
Fig. 14-15 FIFO Configuration Register
RB6
TB6
1: If enabled, the HSCOMOD1 <FDPX1:0> is used to set as follows:
6
6
Reserved
TMP19A61(rev 1.0)14-377
6
0
RB5
TB5
5
5
bytes, RXE is automatically set to "0" to inhibit further
reception.
inhibit further transmission.
are automatically set to "0" to inhibit further transmission and
reception.
Reserved
TB4
RB4
4
5
0
4
TB3
RB3
1: Same as
Bytes used
in RX FIFO
0: Maximum
3
3
Fill level
of RX
FIFO
RFST
4
0
RB2
TB2
R/W
2
2
1: Enable
TX interrupt
for TX FIFO
0: Disable
TFIE
RB1
TB1
3
0
1
1
1: Enable
RX interrupt
for RX FIFO
0: Disable
RB0
TB0
0
0
RFIE
2
0
TMP19A61
(Transmit
BUFFER
＋FIFO)
(Transmit
BUFFER
＋FIFO)
Automatic
disable of
RXE/TXE
0: None
1: Auto
RXTXCNT
disable
1
0
FIFO Enable
0: Disable
1: Enable
CNFG
0
0