tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 345

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Receive data
write timing
Receive data
read timing
(INTRX0 interrupt request)
(INTRX0 interrupt
request)
RBFULL
SCLK0 output
SCLK0 output
RXD0
RXD0
<WBUF> = "1" (if double buffering is enabled) (if data is read from buffer 2)
SCLK output mode
bit
Receiving data
In the SCLK output mode, if SC0MOD2 <WBUF> = "0" and receive double buffering is
disabled, a synchronous clock pulse is output from the SCLK0 pin and the next data is
shifted into receive buffer 1 each time the CPU reads received data. When all the 8 bits
are received, the INTRX0 interrupt is generated.
The first SCLK output can be started by setting the receive enable bit SC0MOD0
<RXE> to "1." If the receive double buffering is enabled with SC0MOD2 <WBUF> set
to "1," the first frame received is moved to receive buffer 2 and receive buffer 1 can
receive the next frame successively. As data is moved from receive buffer 1 to receive
buffer 2, the receive buffer full flag SC0MOD2 <RBFULL> is set to "1" and the INTRX0
interrupt is generated.
While data is in receive buffer 2, if CPU/DMAC cannot read data from receive buffer 2
in time before completing reception of the next 8 bits, the INTRX0 interrupt is not
generated and the SCLK0 clock stops. In this state, reading data from receive buffer 2
allows data in receive buffer 1 to move to receive buffer 2 and thus the INTRX0
interrupt is generated and data reception resumes.
7
<WBUF> = "0" (if double buffering is disabled)
bit 0
bit 0
TMP19A61 (rev1.0)-13-344
bit 1
bit 1
bit 6
bit 6
bit 7
bit 7
TMP19A61
bit 0
bit 0