tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 62

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(Note 1) After overwriting SSCR of the CP0 register, wait for two cycles to allow for register bank
(Note 1) After overwriting SSCR of the CP0 register, wait for two cycles to allow for register bank
(Note 2) Don't access the CP0 register two instructions prior to executing the ERET instruction.
For returning from the interrupt handler to the main process, return the register values saved at the top
of the interrupt handler process and set "0" to INTC ILEV <MLEV> to clear the interrupt mask level. By
executing the ERET instruction after all the return tasks are completed, Status <EXL> of the CP0
register is cleared to "0" and the EPC address returns to PC for the main process to be resumed. If the
shadow register set has been enabled (CP0 register SSCR <SSD> = 0), SSCR <CSS> is updated by
the ERET instruction and the Shadow Register Set number is automatically decremented for
automatically returning the general purpose registers saved in the register bank. If multiple interrupts
are used, it is necessary to set Status <EXL> of the CP0 register to "1" to disable interrupts prior to
executing the return process.
SSCR<CSS>
Examples of interrupt handler settings:
Save from SSCR to stack
NOP instruction
NOP instruction
Save from EPC to stack
Save from Status to stack
NOP instruction
NOP instruction
Status<EXL> =”0”
Example settings to return from the interrupt hander:
Status<EXL> =”1”
ILEV<MLEV> =”0”
SYNC instruction
Return to SSCR
NOP instruction
NOP instruction
Return to EPC
Return to Status
NOP instruction
NOP instruction
ERET instruction
switching before attempting a register access.
switching before attempting a register access.
Returning from the interrupt handler
; Interrupt enable (only for multiple interrupts)
; Interrupt disable (only for multiple interrupts)
TMP19A61(rev1.0)-6-61
; Save SSCR values (as appropriate)
; Stall until SSCR is switched
; Stall until SSCR is switched
; Save EPC values (as appropriate)
; Save Status values (as appropriate)
; Stall before executing ERET instruction
; Stall before executing ERET instruction
; Decrement the mask level
; Stall until mask level is decremented
; Return SSCR values saved (as appropriate)
; Stall until SSCR is switched
; Stall until SSCR is switched
; Return SSCR values saved (as appropriate)
; Return Status values saved (as appropriate)
; Stall before executing ERET instruction
; Stall before executing ERET instruction
; Status<EXL>
=”0”, EPC to PC,
TMP19A61
SSCR<PSS>
to