tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 63

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.9.3
(Note) Some of the registers may be automatically saved and returned by using some interrupt
In "multiple interrupt" processing, a higher interrupt level interrupt is processed while an interrupt is
being processed. With TMP19A61, multiple interrupts are processed through the interrupt priority
arbitration function of INTC. When an interrupt request is accepted, ILEV <CMASK> of INTC is
automatically updated to the interrupt level of the interrupt accepted to enable arbitration to use the
priority preset by the user program.
When an interrupt is accepted, Status <EXL> of the CP0 register is set to "1" disabling further interrupts.
In order to allow multiple interrupts, it is necessary to save the registers that could be overwritten by the
second and the following interrupts before enabling the multiple interrupt process. For this purpose, in
addition to the typical exception handler and interrupt handler processes, save the following registers
before setting Status <EXL> of the CP0 register to "0" to enable interrupts.
Before returning registers in the interrupt return process, it is necessary to disable interrupts using the
method described in Section 6.9.1.4 "Interrupt Disable”. This is to prevent the returned register values
from being corrupted by multiple interrupts. Note that the ERET instruction automatically clears Status
<EXL> of the CP0 register to "0." So, by setting Status <EXL> of the CP0 register to "1" to disable
interrupts in the returning process, you can return from the interrupt with interrupts enabled
automatically.
While there is no significant distinction between the Status <EXL> and Status <IE> parameters, Status
<EXL> is automatically set to "1" upon interrupt generation and cleared to "0" by the ERET instruction
automatically. In saving and returning register values at the initial and final phases of an interrupt
process, where interrupts have to be disabled, hardware controlled Status <EXL> is normally used.
Status <IE> is used for other general interrupt enable/disable control functions.
Applicable interrupt enable/disable control sequences are described in Section 6.9.3.1, “Interrupt
Control for Multiple Interrupts”.
CP0 registers that must be saved:
Example of Multiple Interrupt Setting
function of Toshiba C compiler. Refer to "TX19A C Compiler Reference" provided with the
Toshiba C compiler for more details.
Additional processes required for multiple interrupts
Additional return processes required for multiple interrupts
Proper use of Status <EXL> and Status <IE>
・ EPC
・ SSCR
・ Status
Save the HI, LO, Cause, and Config registers as appropriate.
TMP19A61(rev1.0)-6-62
TMP19A61