tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 324

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Receive buffer 2
Receive buffer 1
Receive interrupt
The following example describes the case a 10-byte data stream is received:
SC0RFC <7:6> = 10: Clears receive FIFO and sets the condition of interrupt generation
SC0RFC <1:0> = 00: Sets the interrupt to be generated at fill level 4.
SC0FCNF <1:0> = 10101: Automatically allows continued reception after reaching the fill
level.
The number of bytes to be used in the receive FIFO is the maximum allowable number.
In this condition, 4-byte data reception may be initiated by setting the half duplex transmission
mode and writing “1” to the RXE bit. After receiving 4 bytes, receive FIFO interrupt is
generated. This setting enables the next data reception as well. The next 4 bytes can be
received before all the data is read from FIFO.
I/O interface mode with SCLK input:
Receive FIFO
RBFLL
RXE
Fig. 13.3.8.2 Receive FIFO Operation
1 byte
TMP19A61 (rev1.0)-13-323
1 byte
2 byte
1 byte
2 byte
3 byte
1 byte
2 byte
3 byte
4 byte
3 byte
1 byte
2 byte
TMP19A61
4 byte
4 byte
3 byte
2 byte
1 byte