tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 367

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.1.10 Transmit Buffer
The transmit buffer (HSC0BUF) is in a dual structure. The double buffering function may be
enabled or disabled by setting the double buffer control bit <WBUF> in serial mode control
register 2 (HSC0MOD2). If double buffering is enabled, data written to Transmit Buffer 2
(HSCOBUF) is moved to Transmit Buffer 1 (shift register).
01), the HINTTX0 transmit interrupt is generated at the same time and the transmit buffer
empty flag <TBEMP> of HSC0MOD2 is set to "1." This flag indicates that Transmit Buffer 2
is now empty and that the next transmit data can be written. When the next data is written to
Transmit Buffer 2, the <TBEMP> flag is cleared to "0."
If the transmit FIFO has been enabled (HSCNFCNF <CNFG> = 1 and <FDPX1:0> = 10/11),
any data in the transmit FIFO is moved to the Transmit Buffer 2 and <TBEMP> flag is
immediately cleared to "0." The CPU writes data to Transmit Buffer 2 or to the transmit
FIFO.
If the transmit FIFO is disabled in the I/O interface HSCLK input mode and if no data is set
in Transmit Buffer 2 before the next frame clock input, which occurs upon completion of
data transmission from Transmit Buffer 1, an under-run error occurs. Then a serial control
register (HSC0CR) <PERR> parity/under-run flag is set.
If the transmit FIFO is enabled in the I/O interface HSCLK input mode, when data
transmission from Transmit Buffer 1 is completed, the Transmit Buffer 2 data is moved to
Transmit Buffer 1 and any data in transmit FIFO is moved to Transmit Buffer 2 at the same
time.
If the transmit FIFO is disabled in the I/O interface HSCLK output mode, when data in
Transmit Buffer 2 is moved to Transmit Buffer 1. When the data transmission is completed,
the HSCLK output stops. So, no under-run errors can be generated.
If the transmit FIFO is enabled in the I/O interface HSCLK output mode, the HSCLK output
stops upon completion of data transmission from Transmit Buffer 1 if there is no valid data
in the transmit FIFO.
If double buffering is disabled, the CPU writes data only to Transmit Buffer 1 and the
transmit interrupt HINTTX0 is generated upon completion of data transmission.
If handshaking with the other side is necessary, set the double buffer control bit <WBUF> to
"0" (disable) to disable Transmit Buffer 2 and do not use the transmit FIFO function.
If the transmit FIFO has been disabled (HSCOFCNF <CNFG> = 0 or 1 and <FDPX1:0> =
(Note) In the I/O interface HSCLK output mode, the HSC0CR <PERR> flag is
insignificant. In this case, the operation is undefined. Therefore, to switch
from the HSCLK output mode to another mode, HSC0CR must be read in
advance to initialize the flag.
TMP19A61(rev. 1.0) 14-366
TMP19A61