tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 40

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.
6.1
Exceptions/Interrupts
The TMP19A61 device is configured with the following 103 maskable interrupt factors and 14
exceptions including NMI. In this section, general exceptions and debug exceptions are described
simply as "exceptions" and interrupts are described as "interrupts."
(INT0~B,KWUP0~3)
The TMP19A61 device not only processes interrupt requests from internal hardware peripherals and
external inputs but also forces transition to exception handling processes as a means of notifying any
error status generated in normal instruction sequences.
By using the register bank called "shadow register set" newly implemented in the TX19A processor core,
it is now unnecessary to save the general purpose register (GPR) contents elsewhere upon interrupt
response thus leading to very fast interrupt response.
The device is capable of handling multiple interrupts according to seven programmable interrupt levels
(priority orders). Also, it can mask interrupt requests with a priority level the same or lower than a
specified mask level.
・General exceptions
・Debug exception
・Interrupts
Overview
Reset exception
Non-maskable interrupt (NMI)
Address error exception (instruction fetch)
Address error exception (load/store)
Bus error exception (instruction fetch)
Bus error exception (data access)
Co-processor unusable exception
Reserved instruction exception
Integer overflow exception
Trap exception
System call exception
Breakpoint exception
Single step exception
Debug breakpoint exception
Maskable software interrupts (2 factors)
Maskable
hardware
TMP19A61(rev1.0)-6-39
interrupts:
85
internal
factors
and
TMP19A61
16
external
factors